Uvm Connect - Session 2 - Connections

UVM Connect Part 2 - Connections - Adam Erickson Verification Technologist - Hello, welcome to Verification Academy. My name is Adam Erickson, Verification Technologist for Mentor Graphics. This is session two, Connections, on the UVM Connect module. So, the agenda for this particular section is that we're going to first reveiw TLM components, where we show implementations of simple SystemC and System Verilog producers and consumers. These components will be independent of UVM Connect, or anything outside their own implementation. We'll then review native TLM connections in SystemC and SystemVerilog testbenches. Then we will introduce the UVM Connect functions which allow you to connect components in SystemC to TLM components in SystemVerilog. And finally we're going to demonstrate how to use those connect functions in simple examples, including both point to point and hierarchical connections.