Back End of Line - Part 1

Now that we have formed our transistors and activated the implants and from silicide the next thing we do is, essentially give it, give this lark to the back end of the line guys. And then their job is to deposit the interconnect layers and form the contacts and complete the rest of the process here. So the first thing that that the backing of the line process dies needs to do is form a contact pug. That is how to contact these. Into the oxide layer. So they etch this contact point, and then the first layer they deposit is actually a titanium layer, that they deposit [UNKNOWN] titanium layer over here. This titanium layer, the purpose of that it's getting layer, so it it gets all the oxygen that was you know, left at the surface. And then oxygen which was, produced on the surface during this etch, and it helps in lowering the contact [INAUDIBLE]. Then the second there, they deposit the conformal trinitride layer. So the deposit of conformal trinitride everywhere. And this trinitride acts as a, acts as a barrier material. So what this trinitride does is it acts as a barrier material. So this trinitride layer is. If it rains, it acts as a barrier, so whatever material we below here, the material that we stops the rain. Stunts them from diffusing it into oxide [INAUDIBLE] unit that It's a precursor with this tungsten extra-fluoride. So which has a high reactivity with both oxygen in the oxide and also with the titanium below. So this this this barrier layer since we prevent that because of from reacting with this outside [INAUDIBLE] also implement the methyl from occurring to the alpha. So once you deposit this [UNKNOWN], then you do a So this tungsten in this CVD deposition it starts in formal CVD depositions. It starts conforming from both sides and then it starts growing and then it starts filling it up with tungsten. And you fill it up from both the sidewalls and you, you keep filling up until they meet in the, the middle and then often the seem forms because it's a c v d process. So there's a seem formed in the tungsten. So these are the different processor involve process steps involved in making this tungsten plug. Let me show this in 3D. So the first thing we do is we start with our nice. Wafer that the front end of the line give to us and then we cover it with a fuller of this, it's covered with fuller of this and then you pattern these holes. So you pack in these holes, which will be acting as a contact plugs and then you etch those holes into the oxide. So you etch those holes in oxide so you can see these holes which are etched into the oxide. The next thing you do is you set it up with titanium over here. So you, you deposit, you spatter a [INAUDIBLE] in there, of titanium. And then you deposit this Ti nitride seal. So this Ti nitride seal, you know, either using CVD or ALD kind of a process, because you want it to be very conformal. So you deposit this con formal Ti nitride seal and it [INAUDIBLE] everywhere. And then the next step you do is you do a CVD, the position of your tungsten so the next thing you do is your CVD of your tungsten which is your plug material. Again, it's a CBD process, so it goes from both your sidewall and you can see it leaves this [UNKNOWN] and and then you, the next thing you do is you polish it off. So you polish off this extra tungsten on the top. You have to polish off this, tinitride in there. And what you're left with are these nice plugs which are now firmware tungsten. The next set of module the, in your backing of the line processor, once you have, done making the, once. Now, then making the blocks [INAUDIBLE] which innately are we are [INAUDIBLE] the next, the next big module is making these interconnect lines. That is making [INAUDIBLE] connect with [INAUDIBLE]. The canister is in your micro processes. So as I described to you earlier, [UNKNOWN] microprocessor has anywhere between 9 to 11 of these micro connect. And the ones which are at the very bottom, they're called as local interconnects. Because they run across short distances. So they just connect nearby transistors and nearby strands then. The one on the very top are pick line when then they are called global interconnects and they typically route the signal between the [INAUDIBLE] forward to microprocessor. And the one in the middle are called intermediate. Immediate level of [UNKNOWN]. And for all these levels of universal equation which determines the delay is that the delay for any of these levels of [UNKNOWN] is proportionate to the resistance of this meta line. Proportional to the resistance of this metaline. And it's also proportional to the capacitor. So it's proportional to the capacitors that this line has. So this sine has with it's adjacent line and what it has with the line at the top and the bottom. So if you need to minimize the DNS of one of the main requirements from the device dies of the circuit dies if you minimize the delay. So there are only two variables that we can play with. We can play to reduce the resistance of this line and we can play to reduce the capacitance of this line. So let's look at how do we reduce the capacitance. So I want to look at from a material perspective how we can reduce the capacitance. The capacitance between these interconnect lines is can be described by this simple equation. Where it's proportional to the height and it is inversely proportional to the distance between these interconnects. So one thing we can play around is with the layout. So we can make these interconnects Shorter, and we can separate them with more distance, and that's one way to change this influence this capacity. But from a material perspective, what we can do is, we can lower the of the dilectric. So, we can lower the k of the dielectric which is separating these two metal lines and that, that is one way we can lower this capacitance. So there are multiple you can try to lower the k. One way is to reduce the density of your silicone oxide. So silicone oxide is, is the lowest scale material. That, we know it has a dialectric constant, or k of 3.9. So, one way you can do is take this silicone oxide and try to make it porous. Or try to reduce its, density to reduce its k value. The other way it can be attempted is to reduce the polarization, or reduce the density of silicon oxide by incorporating other elements into it. So the one way we can lower, so the k value, or the dielectric constant, is proportional to the amount of. Is proportional to the portability of the bond so silicon oxygen has that bond is very polar one way we can reduce the polarization is by introducing carbon so the carbon -oxygen bond. ability and so one way is to reduce the KLs that people introduce other elements into the silicon oxide. So they introduce fluorine and that lowers that gives you some reduction in k. It reduces your k to 3.7. more importantly and more [UNKNOWN] is what is used as you in, introduce these methyl groups. So you introduce a carbon into your film, and that reduces your k value substantially. It reduces your k to 2.8, and that is that is also, it, it's used [UNKNOWN] in the industry. the other way you can reduce the gate is, the ultimate way to reduce the gate is to use air. So, the silicon oxide and that has this [INAUDIBLE] K of 3.9 or 4. Air has a K dielectric constant of 1, and people have What, how they introduce this air in in this back in the line flow is by introducing these air gaps. And in one of the homework problems, we will discuss how to, how the different ways we can introduces a air gap. But shown here is this picture. So you learn the two metal lines. And you have you have air gap between them. So this region is essentially air and that reduces the capacitance between these two metal [UNKNOWN] and this is also used when used regularly in the industries especially applications chips involving memory. Such as flash that has a very regular pattern of lines that has a very regular pattern of lines interconnect lines. red lines and gold lines and air gaps is is used routinely to reduce the, reduce the capacitance between these middle line and also to reduce the capacitance between neighboring seven or .