Uvm Sv Basics 14 - Virtual sequencer - Sequence

Hello my name is Axel Scherer. I will give you a quick introduction into Virtual Sequencers and Sequences. Let’s look back at interface UVC’s sequencers. As you remember, those are tied to a particular protocol; whatever it is standard protocol like AXI or your custom protocol. A big difference to a virtual sequencer is that they are actually not protocol specific; they do not deal with any sequence items. They don’t know what protocol you run. They are abstract in that sense. Another important aspect is that those sequencers are meant to control low-level sequencers so they coordinate traffic amongst lower level sequencers. Most often, those are actually interface UVC sequencers. So if you remember, in an interface UVC we’re taking a sequence, executing them on a sequencer and handing down protocol specific sequence items into a driver. The driver then pushes them into the device. So that’s all good. So we can deal with the particular protocol in an interface UVC. But what are we doing in a real test bench? Here we have a simple abstract test bench with interface a & b, we have the two associated interface UVC’s. How are we going to tell these guys what they should do? That’s the job of the virtual sequencer. It executes a bunch of virtual sequences to coordinate the traffic between different interfaces. Let’s look at some code for this. First we look at the virtual sequencer per say, the device we have here has both UART and APB interfaces, so you can see it has the same class as a interface UVC sequencer. But there’s no difference here, no special plumbing for this virtual sequencer. The only difference you can see here is that it doesn’t have the sequence item parameter put in, so it’s basically protocol agnostic. This particular sequencer is controlling than APB sequencer and a UART sequencer, so those two UVC’s. But other than that, there’s really nothing in the sequencer, everything is built into the library and we are just getting everything for free basically, just by creating this particular sequencer. So let’s look at some virtual sequences. Here we have a particular sequence, it’s also a regular sequence, that is called concurrent,_u2a_a2u. So we want to basically have traffic from the UART to APB and from APB to UART at the same time. That’s the job of this particular sequence. You can have a bunch of fields and constraints to control the execution order just like with regular sequencers. The only difference is we are dealing with a high level of abstraction and coordination amongst different interfaces. And similar to regular sequence, the virtual task body is basically executing the order here. The first thing we’re doing is setting up the device. We are actually configuring the block and this is done with configuration sequence on the APB bus. So before we send any traffic, we to have programmed the device registers accordingly and that’s the job of the virtual sequencer. It says, “Hey, configure first before you do traffic.” So at high level, it does a meaningful order. Once this is completed, it starts the traffic so there is parallel execution, concurrent operations gonna concur. So it hands down, basically, what to do at the APB sequencer and what to do at the UART sequencer. And once it sends out all these transactions on these sequencers, it then has another wrap up sequence, in this case, on the apb bus. So that’s basically it. The virtual sequencer controls and coordinates the traffic amongst lower level sequences, particular in interface UVCs. You can find more videos like this, on this youtube channel or at support.cadence.com at the video library for the Incisive Simulator. Have a great day, thank you very much and talk to you soon.