How to Extract Sram Models

Hello everyone. I'm Ma Long, device modeling application developer at Keysight Technologies. In this short video, I would like to show you how to extract the SRAM models by incorporating cell-level figures of merit. The objectives of this video first to introduce SRAM and its modeling challenges. Secondly, to explain how to optimize transistor model parameters based on device-level characteristics and SRAM cell-level figures of merit all simultaneously. And finally, to show how to download this project file, which I used in this video, so you can use it for your SRAM cell modeling work. First, let's look at some background information. Static random-access memory, SRAM, is a type of semiconductor memory that uses bi-stable latching circuit to store the data. The term static differentiates it from dynamic RAM DRAM, which must be periodically refreshed. SRAM is often used as cache memory for the CPU because of its high speed compared with DRAM. SRAM has lower density and higher cost. In Intel's latest 14 nanometer technology, the cell size only takes up .54 times of the area requires at its 22 nanometer process. Unlike a DRAM memory cell, which is comprise of one transistor and one capacitor, a traditional SRAM cell is comprised of six transistors. Each bit in SRAM is stored on four transistors that form two cross-coupled CMOS inverters. Here, M1 and M2 are called pull down transistors and M5 and M6 are called pull up transistors. The storage cell has two stable states, which are used to denote a logic zero and one. Two additional pass gate transistors, M3 and M4, serve to control the access to a storage cell, during read and write operations. The word line, WL, connects the gate of the pass gate transistors to control their off and on states. While the two complementary bit lines, BL and BL bar are physically connected to the source or drain of the pass gate transistors. An SRAM cell has three different states, standby, read and write. Let's look at them into details. Standby is the state when the circuit is in idle. When the word line is turned off, the PG transistors, M3 and M4, disconnect the cell from the bit lines. The two cross-coupled inverters will continue to reinforce each other as long as they are connected to the supply. Assume that the content of the memory is logic one stored at Q. The read cycle is started by pre-charging both the bit lines to a logic one. Then turning on the word line enabling both the PG transistors. The second step occurs when the values stored in Q and the Q bar are transferred to the bit lines by leaving BL at its precharged value and the discharging BL bar to a logic of zero. Our write cycle begins while applying the value to be written to the bit lines. The word line is turned on and the value that is to be stored is latched in Q node. To realize this operation, careful sizing of the transistors in an SRAM cell, is needed to ensure proper operations. The static noise margin SNM, as measured by the opening in the butterfly curve, has often been used as a metric for SRAM stability. Two drawbacks of the static noise margin, that is the inability to measure it with automatic in line testers and the inability to generate statistical information on SRAM stability fails can be overcome by using the N-curve of the SRAM bit cell. An N-curve is obtained by applying a voltage sweep to the internal storage node, Q, and measuring the resulting current flowing into the same node. Overall, the critical current provides important information of cell stability with respect to transistor sizing and the supply voltage scaling and it can be used as modeling metrics. The N curve can be used to characterize not only cell stability, but also its write-ability. To this end, the critical current for write is used and defined as the lowest current in the N-curve for write which is obtained with one bit line clamped to the ground and the other to the supply voltage. The accurate modeling of SRAM cell is crucial to the cell success. Given the importance of read stability and write-ability in SRAM cell operation, SPICE models of cell transistors not only need to closely fit each transistor's I-V characteristics, but also faithfully reproduce the key figures of merit of the cell as a whole. Consequently, good agreement between silicon data and a SPICE model is required in the critical currents and their behaviors such as the supply voltage and the temperature dependences. It requires the modeling software to be capable of handling multiple device models at the same time. A single window is preferred to display all the fitting targets so as to reduce modeling iterations. Last, all kinds of figures of merit of the SRAM cell should be easily defined and simulated. Now, let me show you a quick example. The cell I will be using will be made available for you to download at the end of this video. Here is the result in IC-CAP. I have organized the window in a way so I and optimize even the models to hit our targets at once. Let me walk through how this project is created. The example includes four models, PD, pull down, PG pass gate, PU, pull up transistor and the SRAM cell. Here, PD, PG and PU are used to get good fitting on the transistor level. Then, we can go to the SRAM model for the final optimization. The model parameters and plots have been cross-referenced among these four models by using the hierarchical structure of IC-CAP itself. You can refer to the additional document that I provide to you at the end of this video to understand the structure and the components of this example. The first step is to obtain the models for each of the cell transistors. Let's use PD as an example. As you can see, a good fitting for IDVD and IDVG is obtained. I would note that if you use the Model Builder Program software to do this extraction, it's possible to transfer the model card and the data to IC CAP. Next, let's define the two figures of merit of the SRAM cell. The critical current for read and the critical current for write. Here, SRAM is defined as the sub-circuit which composes with six transistors. In the setup of N_rd, I have set up the inputs, outputs and their bias conditions used for the N-curve simulation. I can get the N-curve for read in the plots tab. The next step is to get the critical current for read and its bias dependence. Scripts are used here for the customization. In the programing editor window, a small piece of Python code is written. It's used to get the critical current simulation results at different supply voltage values. Then, in the setup of I_rd, I can view the critical current for read versus the supply voltage plot. The blue triangles stand for the measurement and the red solid line stands for the simulation. This is one of the plots that I will fit later. Same thing for the critical current for write. It involves simulating another N-curve at a different bias condition, defining the lowest current in the N-curve as it's value and finally obtaining it's dependency with the supply voltage. Here is my main workspace for SRAM cell modeling. First, I have prepared a window to contain all the plots that I need to fit in the later stage. Second, I have chosen the model parameters set the targets and the regions to optimize. It allows me to run automated optimization on both the transistor level I-V characteristics and the cell circuit level figures of merit at the same time. I could obtain fairly good fitting results in a short time. Furthermore, I could continue to fine tune some model parameters manually for the plot or regions that I care most so as to nail down the model parameters at room temperature. After the model fitting at room temperature, I could continue to optimize the thermal-related model parameters by adding other plots to fit, for example, the critical current versus temperature. If you are challenged by the complexity of SRAM cell modeling, you can download the example I used in this video. Just click the link in the text description associated with this video or by directly using the URL link shown here. You can use this project right away for your SRAM cell modeling work or if you want to customize the project, for example, by adding additional SRAM cell figures of merit in your flow, you shall find it straightforward to do based on this example. Thanks for your time.